1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, which is suited to manufacture of memory cells in DRAM devices, SRAM devices, and the like for use in mobile information terminals such as cellular phones.
2. Description of Related Art
Memory cells in DRAMs or SRAMs used in mobile information terminals especially require MOS transistors that cause a small junction leakage current. FIG. 9 shows a structure of a semiconductor device described in Patent Publication JP-A-2003-17586, as an example of a conventional semiconductor device.
In the semiconductor device 51, a plurality of MOS transistors arranged in the form of pairs of transistors which share a bit line 11 are formed on a semiconductor substrate 31, as shown in the figure. The semiconductor substrate 31 has shallow-trench isolation regions-where an insulating film 12 is filled, and active regions isolated from one another by the element isolation regions. The pair of transistors are formed in a single active region. Each active region is formed in a common p-type well layer 13 to which a substrate potential is applied, and has a p-type channel layer 14 which determines the threshold voltage of the transistors. An n-type buried well layer not shown is formed below the p-type well layer 13.
On both sides of the plug 15 connected to the bit line 11, two gate electrodes 16 each having side spacers 18 are disposed. Each gate electrode 16 is formed on the p-type channel layer 14, with a gate insulating film 17 interposed therebetween. An n-type lightly-doped diffused region 19 which configures a source/drain diffused region is connected to the plug 15 coupled to the bit line 11 or to another plug 15 coupled to a capacitor 20 through a plug 21. The plugs 15 are configured from a polysilicon film doped with phosphorous and fill the contact holes penetrating to the top surface of the p-type channel layer 14 from the top surface of an interlayer dielectric film 22.
In the semiconductor device 51 shown in FIG. 9, phosphorus is implanted to form an electric-field-alleviation layer 91 for the purpose of alleviating the electric fields, after forming the contact holes, in the process of forming the plugs 15. Implantation of phosphorus to alleviate electric fields is generally effected at a depthwise position deeper than the n-type lightly-doped diffused regions 19 as shown in the figure. This technique is described in Patent Publication JP-B-3212150, for example. Interlayer dielectric films 23 and 24, in which the bit line 11 and the plugs 21 are formed, are interposed between the plugs 15 along with the interlayer dielectric film 22 and the capacitors 20.
With respect to the method for manufacturing a semiconductor device, as shown in FIG. 9, a description will now be made particularly of a process of the step of forming the n-type lightly-doped diffused regions 19. After the side surfaces of the gate electrode 16 and the main surface of the semiconductor substrate 31 are thermally oxidized, phosphorus implantation is carried out onto the surface of the semiconductor substrate 31 at a dosage of 2×1013/cm2 and an acceleration energy of 10 KeV, while using this gate electrode structure as a mask. Next, a heat treatment for diffusing implanted phosphorus is carried out to form the n-type lightly-doped diffused regions 19 forming a source/drain diffused region. This heat treatment subsequent to the phosphorus implantation is carried out to serve also to diffusing the dopant, which is implanted to form a lightly-doped diffused regions for transistors in the peripheral circuits, or else the heat treatment is carried out immediately after the phosphorus implantation. In any case, the heat treatment is effected in a nitrogen ambient at a substrate temperature of 900 to 1000° C. for several tens of seconds.
In recent years, miniaturization of memory cells has been progressing more and more because of demands for higher integration of DRAMs. To achieve this miniaturization, the gate length has to be shortened while maintaining the threshold voltage of transistors. The doping density of the channel layer is raised in consistence therewith. Consequently, the junction electric field between the channel layer and the source/drain diffused region becomes large, causing an increase in the junction leakage current, which lowers the data retention capability of memory cells. To reduce the junction leakage current, there are a method of alleviating the electric field strength at the junctions, and another method of reducing vacancy type defects which are the origins of the junction leakage current.
In order to prevent deterioration of the data retention capability, discussions have been made as to various kinds of methods which would reduce the junction leakage current by means of alleviation of electric field strength at the junctions in a source/drain diffused region. For example, Patent Publication JP-B-3212150 proposes that doping density (carrier density) distributions of p-type and n-type layers are set so that the electric field at the junctions might not exceed 1 MV/cm, at which the local Zener effect becomes dominant. However, as further miniaturization of semiconductor devices has been proceeding, the method of reducing the junction leakage current by alleviating electric field strength has come close to the upper limit of itself. This is on the ground that the impurity density has to be higher in the channel layer in order to reduce the gate length while maintaining the threshold voltage of the cell transistors in a semiconductor memory device. However, as the channel-doping density becomes higher, the junction electric field becomes larger accordingly. Hence, much attention is paid to the method of reducing the vacancy type defects in the crystal structure, which remain in the source/drain diffused regions of the silicon substrate.
According to the literature “Defects related to DRAM leakage current studied by electrically detected magnetic resonance”, Physica B, vol. 308-310, pp. 1169-1172, 2001, written by T. Umeda, Y. Mochizuki, K. Okonogi, and K. Hamada, as shown in FIG. 10, it is known that the vacancy type defect includes divacancy plus one or two oxygen atoms within the lattice structure of the silicon substrate, as shown in FIG. 10. The vacancy type defect is also associated with neighboring dangling bonds 52, which are uncoupled bonds of silicon atoms. The vacancy type defects are raised to an energy level within the energy bandgap by the presence of the dangling bonds 52, thereby generating junction leakage-current due to this energy level. The junction leakage current reduces the data retention time of the memory cell, as described before.